1. Field of the Invention
The present invention relates to a semiconductor memory device including read-only memory (ROM) cells, and more particularly to the improvement of the read operation speed thereof.
2. Description of the Related Art
A prior art semiconductor memory device is constructed by a memory cell array including a plurality of ROM cells connected to a plurality of bit lines, a plurality of sense amplifiers each including a MOS transistor connected to one of the bit lines, a reference volatage generating circuit for applying a reference voltage to a gate of the MOS transistor, and a bit line selection circuit for generating a plurality of bit line selection signals for selecting the respective bit lines.
In the above-described prior art ROM device, however, the reference voltage may be decreased due to the capacitive coupling of the gate and source (drain) of the MOS transistor. As a result, the speed of the read operation is decreased. This will be explained later in detail